1. Technical Field
The present invention relates to memory testing, and more specifically, to a memory chip that facilitates memory testing.
2. Related Art
Testing of a memory array in a conventional memory chip using a tester involves running a BIST (Built-In-Self-Test) circuit inside the memory chip through multiple testing passes. For the first testing pass, the tester initializes the BIST and the BIST performs a predetermined sequence of cycles. A cycle may be a write cycle, a read cycle, or a setup cycle. During a write cycle, the BIST writes a test pattern (e.g., all 1s) into a location of the memory array. During a read cycle, the BIST causes the content of a location of the memory array to be read and compared with the expected data. If there is a mismatch, a fail signal is generated to the tester. During a setup cycle, the BIST may do some setup without writing or reading the memory array.
As an example of the testing of the memory array of the conventional memory chip, assume that during the first testing pass, the BIST sequentially and without pause runs from cycle 1d (“d” stands for decimal) to cycle 3000d, in which cycles 1d-2000d are setup and write cycles, and cycles 2001d-3000d are read cycles. Assume further that at cycle 2200d, the read data is not the same as the expected data. As a result, a fail signal is sent to the tester which records the cycle number of the failing cycle (which is 2200d). Assume further that at cycle 2400d, the read data is not the same as the expected data. As a result, a fail signal is sent to the tester which records the cycle number of the failing cycle (which is 2400d).
As a result, the tester has to run the BIST two more testing passes (the second and third testing passes) to collect fail data corresponding to the two failing cycles 2200d and 2400d. More specifically, for the second testing pass, the tester initializes the BIST and the BIST performs the same predetermined sequence of cycles as in the first testing pass except that the BIST stops at cycle 2200d. Then, the read data is collected from the memory chip by scanning out the entire memory chip.
Then, for the third pass, the tester again initializes the BIST and the BIST performs the same predetermined sequence of cycles as in the first testing pass except that the BIST stops at cycle 2400d. Then, the read data is collected from the memory chip by scanning out the entire memory chip.
In general, if during the first testing pass, the tester records N failing cycles, the tester has to cause the BIST to run N more passes. It is always desirable to reduce the number of testing passes the BIST needs to run.
Therefore, a design of a novel memory chip is needed that requires fewer BIST testing passes to test the memory chip than in prior art. A method is also needed for testing the novel memory chip.